Rapid prototyping systems uses Vitex-6 FPGAs for 30 percent speed-up
Embedded.com
April 20, 2010
Synopsys updates the HAPS ASIC prototyping system
Practical Chip Design (EDN)
April 19, 2010
Synopsys Introduces the HAPS-60 Series of Rapid Prototyping Systems
Gabe on EDA
April 19, 2010
For big ASICs, get big FPGAs
Embedded Computing Design
April 19, 2010
Synopsys’ exec details Design Compiler enhancements
EDA DesignLine
April 1, 2010
Design Compiler 2010 doubles productivity of synthesis and place and route
Gabe on EDA
March 29, 2010
A new generation for Design Compiler
Practical Chip Design (EDN)
March 29, 2010
PRODUCT HOW-TO: Automating the FPGA Design Debug Process
Embedded.com
January 20, 2010
Experts At The Table: The Past, Present And Future Of Synthesis
System-Level Design
January 15, 2010
Threaded multicore processing ready for Synopsys’ PrimeTime
EE Times
January 11, 2010
PrimeTime 2009.12 delivers new threaded multicore performance
Gabe on EDA
January 11, 2010
Verification And Software Dominate EDA’s Future
Electronic Design
January 8, 2010
Stacked Dies Gain Attention, but So Far Little Traction
System-Level Design
December 17, 2009
TCAD Enables Robust Process Development and Manufacturing
Semiconductor International
December 16, 2009
Host, device apps get SATA IP solution
EE Times Asia
December 11, 2009
ESL Tools Take Center Stage As Designers Move Up (Best Electronic Design 2009)
Electronic Design
December 6, 2009
Taking power analysis to the transistor level for a full chip
EDN
December 4, 2009
More Choices but Less Design Freedom
System-Level Design
November 19, 2009
Synopsys integrates social media, trade show presences
Inside Technology Marketing
November 10, 2009
Synopsys jumps into ESL-synthesis pool
Electronic Design
October 29, 2009
Living with ambiguity: The other HLS
IC Design and Verification Journal
October 27, 2009
Synthesis at a higher level
Embedded Computing
October 13, 2009
Synphony HLS with unique M-language and model-based solution from Synopsys
EE Herald
October 13, 2009
Synopsys raises synthesis abstraction with M language
EDA DesignLine
October 12, 2009
Synopsys adds high-level synthesis
Chip Design
October 12, 2009
Synopsys Synphony synopsis
harry…the ASIC guy
October 12, 2009
Synopsys’ Synphony acknowledges the Mathworks leadership
Gabe on EDA
October 12, 2009
Combining Formal Verification with Simulation
IC Design and Verification Journal
September 8, 2009
Virtual Prototyping with Simulation for Complex HEV Applications
Power Systems Design Europe
August 31, 2009
As design goes global, tools get more critical
EE Times
August 10, 2009
SystemVerilog and VMM Overcome WiMAX Verification Challenges
Chip Design
August 6, 2009
DAC, EDA AND THE UNBEARABLE LIGHTNESS OF BLOGGING
Greeley’s Ghost
July 31, 2009
What is the future for Intellectual Property?
Practical Chip Design (EDN)
July 29, 2009
Common Platform foundries build links to design to push 32nm
IET
July 28, 2009
Synopsys joins Common Platform, ARM for 32/22nm designs
EE Times
July 27, 2009
Synopsys, ARM Team with IBM, Others in Mobile SoC Design
eWeek
July 27, 2009
Sometimes low-power design means picking the right IP
Practical Chip Design (EDN)
July 23, 2009
Software Confronts New Yield-Management Paradigm
Electronic Design
June 11, 2009
Synopsys Offers Olive Branch
Chip Design
June 10, 2009
Synopsys Catalyst attempts to draw friends, rivals into a common ESL platform
Practical Chip Design (EDN)
June 8, 2009
Synopsys’ new DFM strategy: Focus on in-design verification
Solid State Technology
May 15, 2009
Synopsys rolls IC Validator
EE Times
May 11, 2009
Synopsys IC Validator – Next generation PV
Pallab’s Place (Chip Design)
May 11, 2009
Synopsys IC Validator approach could save many physical design spins
Practical Chip Design (EDN)
May 11, 2009
Synopsys merges IC layout and verification tools
EDN-Europe
May 11, 2009
Converging circuit types demands unified simulation approach
Analog DesignLine Europe
April 7, 2009
Synopsys moves tools to multi-core hosts
Electronics Weekly
April 6, 2009
Synopsys introduces Discovery 2009
Gabe on EDA
April 6, 2009
Multicore, mixed-signal tools take center stage
Chip Design
April 6, 2009
Managers move into the hot seat
Low-Power Design
March 19, 2009
De Geus touts new products, says ICs will rebound
EE Times
March 17, 2009
Synopsys introduces Lynx design system
EDN Asia
March 17, 2009
Synopsys takes wraps off Lynx design system
IQ Online
March 17, 2009
Synopsys Lynx updates Pilot approach to managing an IC design flow
EDN
March 16, 2009
Environment seeks to link EDA tools in one flow
IET
March 16, 2009
Synopsys releases Lynx to manage IC design
EDA DesignLine
March 16, 2009
Synopsys releases hardware-assisted verification offerings
EDA DesignLine
March 9, 2009
Synopsys pulls together its verification platforms
EDN
March 9, 2009
Rapid-Prototyping platform pulls together hardware, software and IP
Electronic Design
March 4, 2009
Virtually Perfect!
New Electronics
January 23, 2009
Filter banks, part 2: Principles and design techniques
DSP DesignLine
January 23, 2009
IP Consolidation Improves Reliability
System Level Design
January 22, 2009
Innovating methodology beyond base classes
EDA DesignLine
January 5, 2009