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View our online webinars and learn from technology experts on a variety of topics. Participate in live webinars, check out the archives, and view product demonstrations. Select a topic below to view online events within each category.

Webinars

32/28nm
Challenges, new technologies, new flows and more
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1/26/2010

32/28nm Design Challenges: The EDA Vendor and Foundry Perspectives

Automotive
Comprehensive design tools for complex automotive design chains
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11/10/2009

Automotive Electronics Reliability: A Software to Silicon Methodology

Circuit Simulation
HSPICE, CustomSim, and other leading AMS technologies
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	3/25/2010	Verify Digitally-Assisted Analog Circuits with CustomSim Fast Transient Analysis

	12/15/2009	CustomSim for Memory Timing & Power Analysis

	9/22/2009	Extraction Techniques to Accelerate High-Capacity Simulation

	4/29/2009	HSPICE StatEye – ISI Predictions Made Easy

	4/28/2009	Increase Design Confidence with CustomSim

Custom Design
Intuitive design with the unified Galaxy Custom Designer environment
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	3/25/2010	Verify Digitally-Assisted Analog Circuits with CustomSim Fast Transient Analysis

	3/23/2010	Custom Designer: Advances in Custom Layout Automation with SmartDRD

	11/11/2009	StarRC Custom Extraction for Custom IC Design

	11/5/2009	HSPICE/Custom Designer for Analog & RF Circuit Design

	11/3/2009	Front-to-Back AMS Flow using Custom Designer

DesignWare IP
USB, PCIe, DDR, HDMI, Audio IP and more
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	2/10/2010	DesignWare IP for AMBA 3 AXI On-Chip Bus

	10/13/2009	Guidelines for Mixed-Signal PHY IP Integration, Debug and Test

	9/23/2009	Reduce Energy Consumption for Datapath Designs

	7/22/2009	SuperSpeed your SoC with USB 3.0

	1/28/2009	Virtualization of PCI Express I/O Devices

FPGA
Optimized tools for complex FPGA design
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	3/3/2010	The Big Design Squeeze: How to get faster design turns in FPGA-based designs

	1/19/2010	Low Power Algorithm Exploration

	3/9/2009	Achieving predictable success in FPGA Projects

Functional Verification
High-performance RTL verification
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	1/27/2010	Transaction-level Debug Using VCS

	11/11/2009	The Recipe for Successful Formal Verification: Proper Constraining of Your Design

	10/27/2009	Achieving 2x Verification Speedup with VCS Multicore

	10/13/2009	VMM: The Next Generation - Delivering Enhanced Ease-of-use, TLM 2.0 Support and Robust Block-to-top Reuse

	8/25/2009	Combining Formal Verification with Simulation: The Best of Both Worlds

In-Design
Physical verification, rail analysis, signoff and more
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	3/24/2010	PrimeRail and IC Compiler: In-Design Rail Analysis for Faster Power Network Design Closure

	3/2/2010	In-Design for Faster Design Closure

	5/20/2009	In-Design PV for Faster Time-to-Tapeout

Low Power
The Eclypse Low Power Solution and other low power technologies
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	1/19/2010	Low Power Algorithm Exploration

	10/1/2009	Fundamentals of Low Power IC Design

Lynx Design System
The Lynx Design System can help lower total cost of design
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6/3/2009

Lynx Product Overview & Demo

Physical Implementation
Accelerate design closure with IC Compiler
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	10/31/2009	IC Compiler Ecosystem

	6/25/2009	Faster Power/Ground Grid Closure with In-Design Rail Analysis

	6/9/2009	Faster Design Closure with Congestion Minimization

	5/20/2009	In-Design PV for Faster Time-to-Tapeout

	3/31/2009	Accelerating Time-to-SI Closure

Rapid Prototyping
At-speed ASIC/ASSP verification using FPGA-based prototypes
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	10/29/2009	Stratix-based Algorithm Acceleration Prototyping

	5/21/2009	FPGA-based Rapid Prototyping: No Assembly Required

Saber
Design and analysis for electronic power, sensing, and actuation
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12/10/2006

Using Simulation to Implement a Robust Design Flow

Signoff
Golden timing signoff, extraction and In-Design Rail Analysis
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	4/7/2010	Improving Your Design Productivity Using Galaxy Constraint Analyzer

	3/24/2010	PrimeRail and IC Compiler: In-Design Rail Analysis for Faster Power Network Design Closure

	2/17/2010	Reducing Design Margins Using PrimeTime Advanced OCV

	1/20/2010	Addressing Signal Integrity Noise in Low Power Design

	11/11/2009	StarRC Custom Extraction for Custom IC Design

Synthesis and Test
Design Compiler, Formality and Test Automation
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	8/5/2009	Boosting Yield and Increasing Quality with Power-Aware Test and Small Delay Defect Testing

	4/21/2009	Successful Equivalence Checking of Highly Optimized DC Ultra Designs

	4/21/2009	Accelerate your design closure with DC Ultra

System-Level Solutions
Enables early software development and algorithm optimization
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	10/14/2009	EDA, ESL and More Ideas from DAC

	7/15/2009	Trends in Software Development- Low Power

	3/12/2009	Embedded Multicore System Development Fundamentals

	12/6/2008	Electronic Systems Level Design (ESL): The Prevailing Method Addressing the Rigors of Advanced Systems Design

TCAD
Simulation tools for technology development and design projects
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	2/24/2010	3-D TCAD Simulation with Sentaurus

	12/1/2009	Simulation of Advanced Semiconductor Devices Including High-k/Metal-gate Transistors and FinFETs

	7/22/2009	Introduction to TCAD Sentaurus New Release Features

	4/15/2009	Simulation of Multi-Junction Solar Cells Using TCAD Sentaurus

	2/4/2009	Thermo Mechanical Finite Element Analysis of 3D Through-silicon Via (TSV) Structures

Seminar Series 2010

Attend a Synopsys technical seminar near you

Webinars

View our online webinars and learn from technology experts on a variety of topics.

SNUG Conferences

Forum for Synopsys users to exchange, discuss and explore ideas

Workshop Series 2010

Hands-on learning from Synopsys experts

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