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View our online webinars and learn from technology experts on a variety of topics. Participate in live webinars, check out the archives, and view product demonstrations. Select a topic below to view online events within each category.

Webinars

32/28/20nm
Challenges, new technologies, new flows and more
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	10/24/2011	Addressing Challenges at 20nm: A Foundry and EDA perspective

	10/13/2010	28nm Silicon and Design Enablement – A Foundry and EDA Vendor Perspective

	9/14/2010	Gold-Standard Extraction at 28nm with StarRC

	8/11/2010	Manufacturing-Aware Routing at 32/28nm

	7/28/2010	Realizing Today’s 32nm and Beyond Large Capacity Designs

Automotive
Comprehensive design tools for complex automotive design chains
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	7/22/2010	Simulation in Photovoltaics with TCAD Sentaurus and Saber

	12/10/2006	Using Simulation to Implement a Robust Design Flow

Best of SNUG
Europe 2010 Webinar Series (SolvNet password required)
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	6/10/2010	Best of SNUG: New In-Design Features (IC Compiler, IC Validator, PrimeRail)

	6/10/2010	Best of SNUG: Generating Low-Power ATPG Patterns using a Shift Power Effort

	6/10/2010	Best of SNUG: Galaxy Constraint Analyzer: Constraint Debugging Made Easy

	5/6/2010	Best of SNUG: Clock Tree Implementation Techniques—A Comparative Analysis

	5/6/2010	Best of SNUG: Simulation Acceleration using Multicore Systems

Circuit Simulation
HSPICE, CustomSim, and other leading AMS technologies
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	11/30/2011	Get the Most from Your HSPICE Simulation

	10/26/2011	Understand and Avoid Electromigration (EM) & IR-drop Effects in Custom IP Blocks

	5/11/2011	Advanced Regression and Analysis for Mixed-Signal Verification Using CustomExplorer Ultra

	5/4/2011	Accurate Jitter and Noise Analysis Using HSPICE Transient Noise Techniques

	1/26/2011	CustomSim and VCS Extend Digital Verification Techniques to Mixed-Signal Designs

Custom Design
Intuitive design with the unified Galaxy Custom Designer environment
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	11/30/2011	Get the Most from Your HSPICE Simulation

	10/26/2011	Understand and Avoid Electromigration (EM) & IR-drop Effects in Custom IP Blocks

	10/19/2011	Use IC Compiler and Custom Designer to Shave Weeks Off Your SoC Development Cycle

	5/11/2011	Advanced Regression and Analysis for Mixed-Signal Verification Using CustomExplorer Ultra

	5/4/2011	Accurate Jitter and Noise Analysis Using HSPICE Transient Noise Techniques

DesignWare IP
USB, PCIe, DDR, HDMI, Audio IP, ARC Processors and more
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	1/10/2012	Reliability and Qualification of MTP NVM IP from Commercial to Automotive Applications

	10/25/2011	Introducing the DesignWare ARC 32-bit Processor Family for Embedded Applications

	10/20/2011	Addressing the Challenges of Designing an AMBA(R)-based SoC with a PCI Express(R) Interface

	10/17/2011	Chinese Version: Build Low-power, high-performance mobile SoCs with complete MIPI solutions

	10/5/2011	Reliability and Qualification of MTP NVM IP from Commercial to Automotive Applications

Formal Equivalence Checking
Comprehensive equivalence checking
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	10/27/2011	Meet Your Schedule with New ECO Verification and Other Enhancements in Formality

	3/15/2011	Successful Formality Equivalency Checking for Low-power Designs – Tips from the Experts

	6/24/2010	New Enhancements for Debugging Inconclusive and Non-Equivalent Verifications in Formality

	4/28/2010	Static Verification Throughout the Low Power Design Flow

	4/21/2009	Successful Equivalence Checking of Highly Optimized DC Ultra Designs

FPGA
Optimized tools for complex FPGA design
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	9/20/2011	Divide and Conquer: Faster FPGA Delivery using Hierarchical, Parallel Design Development

	7/14/2011	Faster, Safer Implementation of High-Reliability, High Availability Designs using FPGAs

	1/20/2011	Team Design for Large FPGA Projects

	3/3/2010	The Big Design Squeeze: How to get faster design turns in FPGA-based designs

	1/19/2010	Low Power Algorithm Exploration

FPGA-Based Prototyping
Accelerate functional verification of ASIC, ASSP and SoC designs
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	1/11/2012	Lowering Validation Costs for Multi-Channel, Wideband Digital Systems Using FPGA-Based Prototyping

	7/21/2011	How to Enable Prototyping of Multi-Million ASIC Gate Designs

	2/24/2011	Advanced Capabilities and Design Interaction with FPGA-Based Prototyping

	3/31/2010	Complementing Emulation with FPGA-Based Prototyping

Functional Verification
High-performance RTL verification
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	9/21/2011	VCS Productivity Technologies - Reducing the Growing Verification Cycle

	7/28/2011	New Advancements in Verification Methodology (VMM and UVM)

	5/11/2011	Advanced Regression and Analysis for Mixed-Signal Verification Using CustomExplorer Ultra

	4/21/2011	New Levels of Productivity for USB 3.0 Verification

	1/19/2011	Using ESP-CV for Faster Redundancy Verification in Memory Designs

In-Design
Physical verification, rail analysis, signoff and more
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	5/5/2010	Eliminating Late-Stage DRC Surprises with In-Design Physical Verification

	3/2/2010	In-Design for Faster Design Closure

	5/20/2009	In-Design PV for Faster Time-to-Tapeout

Low Power
The Eclypse Low Power Solution and other low power technologies
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	10/12/2011	Lighter, Easier and More Flexible Approaches for Multi-Voltage Low Power Design Specification

	6/30/2011	Bringing Up and Optimizing Software Power Management Using Virtual Prototyping

	4/14/2011	Reduce Power Consumption 30% with Advanced Synthesis Techniques

	4/12/2011	From Advanced OCV to UPF: Superior Results with the Lynx Design System

	3/15/2011	Successful Formality Equivalency Checking for Low-power Designs – Tips from the Experts

Low Power Verification
Comprehensive power-aware verification
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	9/15/2010	Power Intent Verification For Low Power Designs Using ESP-CV

	4/28/2010	Static Verification Throughout the Low Power Design Flow

	12/16/2009	Efficient & Accurate Memory Timing & Power Analysis using CustomSim

	8/11/2009	Everything You Always Wanted to Know About Low Power Verification

	8/11/2009	A Structured Methodology for Verifying Low Power Designs

Lynx Design System
The Lynx Design System can help lower total cost of design
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	1/17/2012	Managing Hierarchical, Low Power Design Challenges with the Lynx Design System

	7/19/2011	Optimize in Less Time: Rapid Design Exploration with Lynx Design System

	4/12/2011	From Advanced OCV to UPF: Superior Results with the Lynx Design System

	8/25/2010	Take Control of Your Design With the Lynx Design System

	6/3/2009	Lynx Product Overview & Demo

Manufacturing
Mask synthesis, MDP, lithography simulation and yield management
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	6/28/2011	Using TetraMAX Diagnostics and Yield Explorer for Rapid Failure Analysis

	6/3/2011	Lithography Verification on Advanced Nodes with Proteus LRC

	5/3/2011	Volume Diagnostics for Rapid Yield Ramp at Nanometer Nodes

Physical Implementation
Accelerate design closure with IC Compiler
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	10/19/2011	Use IC Compiler and Custom Designer to Shave Weeks Off Your SoC Development Cycle

	7/20/2011	Save Weeks Fixing ECOs with PrimeTime and IC Compiler

	7/19/2011	Optimize in Less Time: Rapid Design Exploration with Lynx Design System

	10/13/2010	28nm Silicon and Design Enablement – A Foundry and EDA Vendor Perspective

	8/11/2010	Manufacturing-Aware Routing at 32/28nm

RTL Synthesis
Industry’s most comprehensive synthesis solutions
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	11/1/2011	Expediting Design Schedules with DC Explorer - Qualcomm’s Experience

	10/27/2011	Meet Your Schedule with New ECO Verification and Other Enhancements in Formality

	10/12/2011	Lighter, Easier and More Flexible Approaches for Multi-Voltage Low Power Design Specification

	4/27/2011	Harness the Power of SystemVerilog with Design Compiler to Increase Productivity

	4/14/2011	Reduce Power Consumption 30% with Advanced Synthesis Techniques

Saber
Design and analysis for electronic power, sensing, and actuation
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	7/22/2010	Simulation in Photovoltaics with TCAD Sentaurus and Saber

	12/10/2006	Using Simulation to Implement a Robust Design Flow

Signoff
Golden timing signoff, extraction and In-Design Rail Analysis
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	10/25/2011	Faster Clock Analysis and Debug

	10/20/2011	Extraction Features & PDKs for Accurate Analog Design

	7/20/2011	Save Weeks Fixing ECOs with PrimeTime and IC Compiler

	5/18/2011	Fast Timing Constraint Cleanup with Galaxy Constraint Analyzer

	4/26/2011	StarRC High Performance Multicore and Hierarchical Extraction

System-Level Solutions
Enables early software development and algorithm optimization
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	2/28/2012	Programmable Hardware Accelerators Made Easy: Implementing Custom Processors without Compromising Performance, Power or Area

	1/11/2012	Lowering Validation Costs for Multi-Channel, Wideband Digital Systems Using FPGA-Based Prototyping

	11/15/2011	LTE-A Physical Layer Design: Downlink

	11/3/2011	Using High-Level Synthesis to Streamline ASIC Multi-Rate Communications Design

	10/13/2011	Using High-Level Synthesis and Open Source Imaging Libraries to Streamline ASIC/FPGA IP Development

System-to-Silicon Verification
Comprehensive Verification Solution spanning all design domains
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	11/30/2011	Get the Most from Your HSPICE Simulation

	6/30/2011	Bringing Up and Optimizing Software Power Management Using Virtual Prototyping

	5/5/2011	Closing the Verification Gap: Integrating Algorithm and RTL Verification for Signal-Processing Apps

	3/31/2010	Complementing Emulation with FPGA-Based Prototyping

	3/25/2010	Verify Digitally-Assisted Analog Circuits with CustomSim Fast Transient Analysis

TCAD
Simulation tools for technology development and design projects
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	10/6/2011	New Features in TCAD Sentaurus: September 2011 Release

	6/1/2011	Modeling Semiconductor Device Variability with TCAD Sentaurus

	3/30/2011	Modeling Semiconductor Reliability with TCAD Sentaurus

	1/18/2011	New Features in TCAD Sentaurus: December 2010 Release

	7/30/2010	Simulation of Power Devices with TCAD Sentaurus

Test Automation
Integrated test and yield analysis solution
more

	6/28/2011	Using TetraMAX Diagnostics and Yield Explorer for Rapid Failure Analysis

	5/3/2011	Volume Diagnostics for Rapid Yield Ramp at Nanometer Nodes

	4/21/2010	Reducing the Cost of Pin-Limited Test Using DFTMAX Compression

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