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| User Papers and Presentations |
| A1 User Session: Front-to-Back Implementation |
Advanced Design Flow for LPDDR2 non Volatile Memory Design (Technical Committee Award)
Author(s): Anna Faldarini, Christophe Laurent [Micron Technology] |
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Advanced Design Flow: Design of a Full-HD120 Video Accelerator from a C Architecture to an ICC Implementation
Author(s): Alexandre Bleys [ST-Ericsson] |
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Design Optimization and Formal Checking with Retiming Techniques (Technical Committee Award Honorable Mention)
Author(s): Philippe Maneta [ST-Ericsson] |
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| A2 User Session: Low-Power Verification |
Dynamic Low-Power Verification on a Multi-CPU Subsystem using VCS-NLP
Author(s): Massimo Calligaro [ST-Ericsson] |
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Formal and Low-Power Verification on Large SoC Designs
Author(s): Yassine EL Khourassani [ST-Ericsson] |
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Real Voltage Modeling through Assertions (2nd Place - Best Paper)
Author(s): Ankita Arya, Mohit Jain, Chandan Singh [STMicroelectronics] |
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| A3 User & Tutorial Session: Hierarchical Design & Floorplanning |
Hierarchical Design-Planning of a Multi-million Instance Design
Author(s): Rashid Iqbal [Intel] |
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ICC Template-Based Power Network Synthesis (TPNS) & Power Network Analysis (PNA) to Increase Implementation and Verification Efficiency of Mixed-Signal Design Multi-Voltage Power Ground Grids
Author(s): Christelle Leherpeur [STMicroelectronics] |
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| A4 User Session: Design for Test and ATPG I |
Early Power Analysis Methodology using PrimeTime PX to Assess Achievable Maximum Shift Frequency before ATPG
Author(s): Jean-Michel Lagoutte [ST-Ericsson], Philippe Rossant [Synopsys France] |
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State-of-the-Art, Low-Power DFT Methodology
Author(s): Swapnil Bahl, Shray Khullar, Roberto Mattiuzzo, Saverio Graniello [STMicroelectronics] |
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Using TetraMax Top Level Protocol Generation to Extract DFTMAX Codec Information for Lifetest Pattern Generation (HTOL) (3rd Place - Best Paper)
Author(s): Gerald Briat, Stéphane Guilhot [ST-Ericsson], Philippe Rossant [Synopsys] |
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| A5 User and Tutorial Session: FPGA Implementation |
Implementing Dual Role Device USB2/3 IP from Synopsys using the HAPS6x Platform
Author(s): Nicolas Krohmer [Texas Instrument] |
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| A6 User Session: AMS Verification and Sign-off |
Case Study: Correlating PrimeTime with SPICE
Author(s): Casey McCoy [Atmel Corporation] |
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Groundbreaking SQL Method to Analyze Circuit Check Reports
Author(s): Pierluigi Daglio, Salvatore Santapa, Alessandro Valerio [STMicroelectronics] |
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Methodology for ST NVM Technologies Description Turned to Interconnect Parasitic Extraction with StarRC and to the Memory Cell Characterization with Rapid3D
Author(s): Marina Gratarola, Silvia Lesma, Luca Togni [STMicroelectronics], Claudio Rallo [Synopsys] |
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| B2 User & Tutorial Session: Testbench and Verification IP |
A Beginner’s Guide to Using SystemC TLM-2.0 IP with UVM
Author(s): John Aynsley, David Long, Doug Smith [Doulos] |
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| B3 User and Combo Session: Clock Tree Synthesis & Sign-off |
Asic Compliance CTMesh Solution
Author(s): Boon Chong Ang, Phooi Choong Loh [Intel] |
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| B4 User & Tutorial Session: Design for Test and ATPG II |
Efficient Flow for the Debug of Compressed Scan Patterns During Serial Simulations (1st Place - Best Paper, Best Paper Award)
Author(s): Sébastien Rousset, Mathieu Thomas [Scaleo Chip] |
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| B5 User White Paper and Tutorial Session: Advanced FPGA Design Techniques |
FPGA Hierarchical Design Techniques using Synopsys SynplifyPremier and Xilinx PlanAhead
Author(s): James McLenaghan [Xilinx], Xavier Mathes [Synopsys] |
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| B6 User and Tutorial/Demo Session: Digital/Analog Co-Design |
Bridging the Digital/Analog Gap in Design Implementation
Author(s): Giuseppe Conti [STMicroelectronics], Giuseppe Contarino [Synopsys Italy] |
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| C1 User & Tutorial Session: RTL Synthesis |
An All-Inclusive Solution for Clock Domain Crossings
Author(s): Charles Laurent, Phuong Nguyen, Joseph Dekoker, Domenique Spagnuolo [Sigma Designs] |
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| C3 User & Tutorial Session: Design Closure |
Implementing an High-Performance Graphic Core with Synopsys Galaxy Platform in a Fast and Predictable Turnaround Time
Author(s): Pascal Teissier [STMicroelectronics] |
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| C4 User, Tutorial and R&D Session: Advanced Test Techniques |
Custom LBIST Integration in an Automotive Design
Author(s): Marzia Annovazzi, Marcello Raimondi [STMicroelectronics] |