In Verification, Physics Intrudes Forcefully At 28 nm Electronic Design
December 21. 2010
To Err Is Universal Electronic Engineering Journal
December 14, 2010
The Deafening Problem Of High-Speed I/O Low-Power Engineering Community
December 2, 2010
Synopsys beats analysts’ expectations EE Times
December 1, 2010
LightTools enhances lighting design capabilities for the development of luminaires Electronics World
November 19, 2010
TSMC qualifies Synopsys' IC Validator for 40nm, 65nm EE Times
November 17, 2010
Synopsys in Armenia Among Twelve Finalists to Receive U.S. Secretary of State's 2010 Award for Corporate Excellence Gabe on EDA
November 11, 2010
Is social media really helping semicon/VLSI firms? Pradeep’s Point
November 10, 2010
Synopsys debuts DesignWare STAR ECC IP Test & Measurement World
November 6, 2010
Carl Zeiss and Synopsys Collaborate on Die Metrology Chip Design
October 28, 2010
Himax licenses Synopsys' Galaxy, Discovery tools EE Times
October 26, 2010
100 Tapeouts Underscore Rapid and Broad Acceptance of Synopsys' In-Design Physical Verification Gabe on EDA
October 12, 2010
Synopsys acquires Optical Research Associates SPIE
October 11, 2010
EDA Focus: HSPICE Enhances Speed and Capacity Microwave Journal
October 9, 2010
Synopsys adds to consolidation trend Optics.org
October 8, 2010
Synopsys makes optical design software foray CIOL
October 8, 2010
Making Too Much Noise Low-Power Engineering Community
October 7, 2010
Paradox of Pursuit; Synplify Saves Synthesis - Again FPGA & Programmable Logic Journal
September 29, 2010
Synopsys enhances FPGA synthesis – 4X speedup plus team design capabilities Programmable Logic DesignLine
September 27, 2010
Software Drives Design Requirements System-Level Design Community
September 23, 2010
Moving To Open-Source Software System-Level Design Community
September 23, 2010
HSPICE 2010 advanced analysis features provide a high-performance analog verification solution EE Times (Design)
September 20, 2010
Simulation gets 7X speed boost New Electronics
September 20, 2010
Synopsys wraps $315M acquisition of Virage Logic Yahoo! Finance
September 2, 2010
Using In-Design Physical Verification to Reduce Tapeout Schedules EE Times (Design)
July 30, 2010
ESL Requires New Approaches To Design And Verification System-Level Design Community
July 22, 2010
Extracting a life IC Design and Verification Journal
July 13, 2010
TLM-Based Verification Finds Strength In Standards Electronic Design
June 22, 2010
PrimeTime 2010 scales timing analysis beyond 500 million instances Gabe on EDA
June 14, 2010
Synopsys tunes back-end tools for DAC EDN
June 14, 2010
Wow! PrimeTime 2010 scales STA beyond 500 million instances! TechBites
June 14, 2010
Block reuse to speed up chip-level timing analysis IET
June 14, 2010
Rapid prototyping systems uses Vitex-6 FPGAs for 30 percent speed-up
Embedded.com
April 20, 2010
Synopsys updates the HAPS ASIC prototyping system
Practical Chip Design (EDN)
April 19, 2010
Synopsys Introduces the HAPS-60 Series of Rapid Prototyping Systems
Gabe on EDA
April 19, 2010
For big ASICs, get big FPGAs
Embedded Computing Design
April 19, 2010
Synopsys’ exec details Design Compiler enhancements
EDA DesignLine
April 1, 2010
Design Compiler 2010 doubles productivity of synthesis and place and route
Gabe on EDA
March 29, 2010
A new generation for Design Compiler
Practical Chip Design (EDN)
March 29, 2010
PRODUCT HOW-TO: Automating the FPGA Design Debug Process
Embedded.com
January 20, 2010
Experts At The Table: The Past, Present And Future Of Synthesis
System-Level Design
January 15, 2010
Threaded multicore processing ready for Synopsys’ PrimeTime
EE Times
January 11, 2010
PrimeTime 2009.12 delivers new threaded multicore performance
Gabe on EDA
January 11, 2010
Verification And Software Dominate EDA’s Future
Electronic Design
January 8, 2010